Bachelor's degree in Computer Science or equivalent. With a minimum of 8+ years of experience.

As a Senior Verification Engineer, you will verify the design and implementation of leading SoC design for the automotive space. In this position, you will be a member of the verification team responsible for full-chip verification spanning the following areas: ASIC design, architecture, golden models and micro-architecture.

Essential Functions:
•Creation and execution of verification plans from internal specifications, external IP and in coordination with architects and designers
•Creation and deployment of automated flows for block and chip-level verification and coverage collections, for Data path, DSP and SoC subsystems
•Develop Verilog, System Verilog, UVM test environments, including models of analog component and external components/models
•Architecture, design and troubleshoot UVM verification components, environments and scripts
•Working with analog and digital team members to debug failures, manage bug tracking, and achieve the high code, functional and system-level coverage needed for automotive products.
•Hold detailed verification reviews and set the standard for coding quality
•Integrate 3rd party VIP and test case into system-level suites
•Test planning development and regression setup using either python/Perl/TCL scripts
•Planning, execution and debug of gate-level simulations for functional, DFT verification and power analysis
•Plan, develop and deploy FPGA based verification systems (Xilinx/Protium) to augment and complete verification requirements and support early software development
•Work closely on pre-tape-out verification on simulation and emulation platforms, as well as silicon bring up, debug and optimization
•Work as part of an agile digital team to ensure first silicon success

Required Education and Experience:
•BS degree in EE/CS with ~8 years of relevant experience
•Advanced knowledge of HVL methodology (UVM/OVM/VMM)
•Solid verification skills in problem-solving, constrained random testing and debugging.
•Knowledge of industry-standard interfaces (Gigabit Ethernet, UART, I2C, QSPI)
•Expert in System Verilog, UVM should have independently created UVM based verification environments from scratch
•Experience in working with multi-site development teams
•Proven success in the unit, sub-system and SoC verification
•Hands-on experience with Gate level simulations, SDFs, Gate level simulation debug
•Experience with industry-standard verification tools, VIP/AVIP integration and configuration in test benches
•Should be a great teammate with excellent communication skills and the desire to take on diverse challenges
•Any exposure to Functional Safety verification is a plus
•Any experience with FPGA based verification/development with Protium is a plus
•Able to understand and debug RTL code
•Matlab experience is a plus
•Experience with System Verilog Assertions (SVA) a plus
•Experience writing scripts in Perl/Python
•Programming experience in C/C++ a plus