Key Responsibilities

• Partition and map multi-million gate SoC designs to FPGA prototyping platforms (e.g., HAPS, Zebu, Cadence Z2).
• Create and validate design partitions, FPGA builds, and simulation testbenches for individual components.
• Set up and maintain prototyping systems in the lab, ensuring robust bring-up and ongoing support.
• Define and enhance prototyping methodologies to streamline and optimize the development flow.
• Optionally contribute to block-level RTL design and top-level IP integration.
• Collaborate cross-functionally with software, verification, and hardware teams to validate functional and performance metrics.

Requirements

• Bachelor’s degree in Electrical or Computer Engineering with a minimum of 10 years of ASIC or FPGA experience, or a Master’s degree with at least 8 years of relevant experience.
• Deep expertise in FPGA design, including partitioning complex designs across multiple FPGAs.
• Hands-on experience with synthesis, place-and-route, and timing closure for FPGAs.
• Strong understanding of digital design fundamentals, including Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC).
• Proficient in Verilog/SystemVerilog RTL coding and third-party IP integration.
• Methodical and detail-oriented approach to debugging and root-cause analysis during FPGA development.
• Full working knowledge of the Synopsys HAPS prototyping flow, beyond image building.
• Proven experience in HAPS bring-up, including hardware setup and troubleshooting.

Preferred Qualifications

• Experience prototyping Networking SoCs on HAPS, Cadence Z2, or Zebu platforms.
• Familiarity with protocols such as PCIe, DDR, Ethernet, and various networking standards.
• Experience prototyping ARM or RISC-V CPU architectures.
• Advanced scripting skills using TCL, Python, or Perl to automate flows and diagnostics.

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