Principal Design Verification Engineer

We are seeking an experienced Principal Design Verification Engineer to lead verification activities for complex SoC designs. The ideal candidate will architect and develop advanced verification environments, create comprehensive test plans, and collaborate with cross-functional teams to ensure high-quality silicon delivery.

Primary Responsibilities

* Lead design verification for complex SoC and ASIC projects through successful tape-out.
* Develop verification architectures, UVM-based environments, reference models, and bus-functional components.
* Create detailed verification test plans using constrained-random methodologies and coverage analysis.
* Develop and execute verification tests to achieve functional coverage goals.
* Debug design failures and work closely with design engineers to resolve issues.
* Develop and maintain automation tools and scripts to improve verification efficiency.
* Support regression testing and continuous verification processes.
* Mentor junior engineers and provide technical leadership on verification projects.

Required Qualifications

* Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field. 
* Proven experience leading Design Verification activities for complex SoC/ASIC tape-outs.
* 10+ years of design verification experience; or a Master's/Ph.D. with 5+ years of relevant experience
* Experience developing directed and constrained-random verification environments.
* Proficiency with Python or Perl scripting and EDA verification tools.
* Strong understanding of object-oriented programming concepts.
* Experience working in Linux environments.
* Programming skills in C++; ARM assembly knowledge is a plus.
* Strong expertise in SystemVerilog and UVM.

Preferred Qualifications

* Experience with networking protocols.
* Experience verifying multi-core SoCs.
* Ability to work in a fast-paced environment and lead cross-functional verification efforts.
* Semiconductor industry experience.

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