Key responsibilities include:
•Hands-on responsibility from synthesis to place and route of a SOC block through signoff flows including timing and physical verification
•Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment
•Interact with RTL counterpart and SOC team to develop timing constraints and resolve design issues pertaining to block closure

Minimum requirements:
•BSEE, Computer Engineer or comparable and 3 + years of experience

Skills 
•Solid understanding and working knowledge of the SOC/ASIC design flow with some experience in taping out designs
•Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools
•Experience in block level floor-planning, implementing power grid and area/congestion optimization
•Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python
•Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail
•Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must

Preferred candidate will possess the following:
•Experience with 16nm Finfet or smaller process nodes
•Understanding of multi-voltage and power gated implementation and associated power domain checks
•Hands-on experience with clock tree synthesis (CTS) on designs with multiple clock domains
•Strong working knowledge of formal equivalency checks, LP checks, timing constraints, UPF
•Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage