Design Verification Engineer (ASIC Design Verification)

  • Salary

    $105,000 - $115,000 Per Year

Experience

3 to 10 Years

Posted On

Apr 21, 2023

Company

2T Consulting

Travel Requirements

0%

Job Overview

Required Skills

  • System Verilog
  • UVM
  • Verilog
  • ASIC design verification

Job Type

Full-time

Location

San Jose, CA

Job Description

Technical / Functional Skills

  • At least 4 years of experience with pre-silicon DV (Design Verification)
  • Must have hands-on experience with writing code using System Verilog and UVM over the past 2 years. 
  • Must be a quick learner, independent and communicate well. 
  • Knowledge and hands on experience with Verilog, System Verilog, UVM, debugging waveforms. 
  • Experience with verification of networking products and networking background. 

 

Roles & Responsibilities

  • Building a testbench for a medium complexity block using System Verilog and UVM
  • Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM.
  • Debugging tests with design engineers to deliver functionally correct design blocks
  • OOPS, randomization, constraints, interfaces
  • Writing & analyzing functional coverage, assertions
  • Generating and analyzing code coverage & writing waivers

Job ID: 2C230055

  • Posted By

    Sheri F Weaver

Designation

Sr. Recruiter

Company

2T Consulting

Last Login

Apr 22, 2024

Posted On

Apr 21, 2023


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