Key Responsibilities

• Lead the timing analysis and closure of high-performance ASIC designs, ensuring all timing requirements are met.
• Develop block and SoC timing constraints, setup, and full-chip STA signoff for multi-corner, multi-voltage designs.
• Own the timing flow and execution, ensuring timing budgets, repeater planning, and constraint generation/exceptions are properly managed.
• Work closely with block and SoC design teams to understand timing constraints, design requirements, and convergence challenges.
• Partner with physical implementation teams to debug and resolve timing failures, ensuring designs meet Quality of Results (QoR) objectives.

Qualifications & Skills

• 10+ years of experience in ASIC design, with a focus on STA and CAD methodology for high-performance designs.
• Strong knowledge of timing closure, multi-corner/multi-voltage STA setups, and signoff processes.
• Expertise in timing budgeting, repeater planning, and constraint generation.
• Experience working with both design and physical implementation teams to resolve timing issues and ensure successful SoC signoff.
• Excellent communication and collaboration skills to effectively engage cross-functional teams.

Preferred Skills

• Experience with advanced EDA tools for timing analysis and physical design.
• Familiarity with scripting languages for automation and flow optimization.

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