Job Requirements

• 10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high-performance designs.
• ASIC STA and CAD Methodology Expertise for High-Performance Design Implementation and Timing Closure
• Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs.
• Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
• Engaging closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges.
• Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures

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