ASIC Designer

  • Salary

    $160,000 - $200,000 Per Year

Experience

to Years

Posted On

Aug 18, 2022

Company

PB Consulting

Travel Requirements

N/A

Job Overview

Required Skills

  • Verilog
  • SystemVerilog
  • Self motivated
  • Scripting
  • SSD
  • SAP ERP
  • RTL
  • Python
  • Physical data model
  • Perl
  • PCI Express
  • NAND
  • MOST
  • Interfaces
  • IP
  • Firmware
  • FPGA
  • Electrical engineering
  • Documentation
  • Design engineering
  • Debugging
  • DDR SDRAM
  • Computer science
  • Communication skills
  • C
  • Architecture
  • ASIC

Job Type

Full-time

Location

San Jose, CA

Job Description
  • Master degree or better in Electrical Engineering or Computer Science
  • 5+ years of experience working on ASIC design and development.
  • Experience in micro-architecture and RTL development of complex designs in Verilog.
  • Understanding of ASIC design flow including RTL design, verification synthesis timing, ECO, bring up and lab debug.
  • Experience with multiple clock domains and asynchronous interfaces.
  • Strong Verilog RTL, C/C++ skills
  • Prior experience or knowledge of PCIe, NVME, DDR, ECC and NAND is a highly desirable
  • Some Perl or Python scripting experience
  • System Verilog would be a plus but not required
  • Strong written and verbal communication skills
  • Self-starter, good team player, ready to work in a dynamic and rewarding environment

Job ID: PC220180

  • Posted By

    William Christopher

Designation

Sr. Manager

Company

PB consulting

Last Login

Apr 18, 2024

Posted On

Aug 18, 2022

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