· Should be self-motivated in order to achieve assigned objectives with minimal supervision.

· Experience in RTL (Verilog or VHDL), OpenCL or other system level languages a plus.architecture, design, coding, simulating, and debugging FPGA on actual HW.

· Develop micro architecture documents, participate in micro architecture reviews and complete the RTL design, verification, synthesis and timing verification closure.

· Generating the component requirements and specifications, defining top-level architecture as well as micro architecture for detailed implementation, developing Verilog / system verilog code, defining verification methodology, building a test bench for self-checking verification, performing detailed synthesis, timing analysis, and analysis of system level functionality.