Asic Design Manager

  • Salary

    N/A

Experience

to Years

Posted On

Aug 14, 2022

Company

PB Consulting

Travel Requirements

N/A

Job Overview

Required Skills

  • RTL Coding
  • ASIC

Job Type

Full-time

Work Authorization

N/A

Location

Campbell, CA

Job Description

· Should be self-motivated in order to achieve assigned objectives with minimal supervision.

· Experience in RTL (Verilog or VHDL), OpenCL or other system level languages a plus.architecture, design, coding, simulating, and debugging FPGA on actual HW.

· Develop micro architecture documents, participate in micro architecture reviews and complete the RTL design, verification, synthesis and timing verification closure.

· Generating the component requirements and specifications, defining top-level architecture as well as micro architecture for detailed implementation, developing Verilog / system verilog code, defining verification methodology, building a test bench for self-checking verification, performing detailed synthesis, timing analysis, and analysis of system level functionality.

 

 


Job ID: PC220177

  • Posted By

    William Christopher

Designation

Sr. Manager

Company

PB consulting

Last Login

Mar 04, 2024

Posted On

Aug 14, 2022


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