· We have a need for an experienced and growth minded mission engineer. This engineer will be responsible for the DC power integrity (EM/IR) methodology and analysis of a complex ASIC using the Cadence Voltus tools under the FX14 Marvell ASIC flow (DFlow). This individual would also be a part of the doing detailed Power Estimations and simulations of the ASIC.

· Prior experience with the Marvell FX14 ASIC chip design flow is requirement for this position using the Cadence design environment and an intimate knowledge/use of scripting languages such as TCL is required.

· The selected candidate will be required to work both independently and collaboratively in conjunction with other teams across IBM. As such, the ability to be a hands-on person is critical, capable of running tools, while working effectively with others, while having the willingness and ability to learn new tools.

Task Description:

Job Duty 1 setup, run, and debug (read/write tcl scripts, as needed) Cadence Voltus EM/IR analysis for a complex FX14 ASIC

Job Duty 2 - Work with team to execute detailed VCD enabled power estimates and simulations for a complex FX14 ASIC

Required skills/Level of Experience :

ASIC Design Engineer – power integrity design flow expert – Electrical / Computer Engineer

At least 5 years of experience.